A Georgia Tech spinout called Nagare Labs has unveiled a new memory architecture designed to address the growing bandwidth constraints in artificial intelligence computing. The company, which counts former Intel CEO Pat Gelsinger on its board, says its Z2RAM technology can place memory with the speed of static random access memory (SRAM) directly on top of AI processors. This approach aims to match the high capacity of dynamic random access memory (DRAM) without the traditional heat and latency penalties.
Overcoming Thermal and Density Limits
AI accelerators require massive data throughput, but current high-bandwidth memory solutions struggle to keep pace. Manufacturers often face yield issues when producing stacked memory layers, and heat generation remains a significant barrier. Samsung, for instance, has limited its zHBM plans to approximately four layers due to thermal concerns. Micron has also adjusted its vHBM designs to include heat-spreading structures to keep memory temperatures below 95 degrees Celsius.
Nagare Labs proposes a different path. The company describes Z2RAM as a capacitorless design using two transistors and a shield. A write transistor places a charge on a storage node while a shield blocks interference from neighboring cells. The read transistor senses the charge without draining it, allowing for non-destructive reads. This eliminates the need for the frequent write-back cycles required by standard DRAM.
The company projects that its first-generation product will offer five times the density of SRAM using six stacked layers. It also claims 14 times the speed of DRAM and three times less energy per read operation. These figures are based on simulations and early prototype testing rather than mass-produced silicon.
Retention and Manufacturing Challenges
Retaining data at high temperatures is a primary hurdle for any memory placed directly on a hot processor. Founders of Nagare Labs have published papers showing improvements in retention times. A 2025 study demonstrated a cell that held data for over 1,000 seconds at 25 degrees Celsius. More recently, the team reported a boosted three-transistor cell that retained data for more than 300 seconds at 85 degrees Celsius. While this exceeds the refresh intervals needed for most AI workloads, it still falls short of the 95-degree threshold where standard DRAM must operate.
Manufacturing Z2RAM involves depositing layers directly onto the accelerator die. Nagare Labs states that it uses standard 300 mm tools with deep ultraviolet (DUV) lithography, avoiding the need for expensive extreme ultraviolet (EUV) equipment. The process aims to pattern multiple layers in a single exposure, potentially allowing for over 100 layers in future versions.
Despite these technical claims, the company acknowledges significant obstacles. Nagare Labs currently lacks a fabrication facility and relies on university clean rooms for prototyping. The founders are seeking an R&D fab partner to scale production. They also face the challenge of defining new interface standards for integrating this memory with existing accelerators. Reliability issues, such as single-electron effects shifting cell thresholds, remain unresolved.
Pat Gelsinger, who previously led Intel through the development and eventual discontinuation of Optane memory, is now backing this effort through Playground Global. His involvement highlights the ongoing industry search for a solution that bridges the gap between slow storage and fast memory. Nagare Labs targets sampling of Z2RAM tiles within four years, with production shipments potentially arriving within the next decade.
Source: Tom’s Hardware
